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Quarterly published in print and online "Inventi Impact: VLSI" publishes high quality unpublished as well as high impact pre-published research and reviews catering to the needs of researchers and professionals. The journal covers all recent advances in very large scale integration. The focus areas are: VLSI circuits; low power and power-aware designs; testing, reliability & fault-tolerance; emerging technologies; VLSI applications; nano electronics, molecular, biological and quantum computing; and, wireless communications.
In the IoT/wearable devices, the antenna is shared with the receiver and transmitter of the\ntransceiver. This requires the control of the switch between the antenna and the control circuitry to\nachieve both low insertion loss and high isolation. This paper presents a low insertion loss and high\nisolation switch based on Single Pole Double Throw (SPDT) switch for 2.4 GHz Bluetooth low power\n(BLE) transceiver. The body-floating technique is used to improve the insertion lossâ??s performance.\nAn ultra-small on-chip matching network with high Q-factor is proposed. The shunt transistors\nare used as active shunt capacitors that create the active matching network to improve isolation\ncharacteristics. The proposed SDPT switch was designed using 55 nm CMOS process with the total....................
This paper presents the design, fabrication, and electrical characterization of an\nelectrostatically actuated and capacitive sensed...plate resonator structure that exhibits a\npredicted mass sensitivity of.... The resonator is embedded in a fully on-chip\nPierce oscillator scheme, thus obtaining a quasi-digital output sensor with a short-term frequency\nstability of....(...) n air conditions, corresponding to an equivalent mass noise floor as\nlow as.... The monolithic CMOS-MEMS sensor device is fabricated using a commercial..... metal complementary metal-oxide-semiconductor (CMOS) process, thus featuring\nlow cost, batch production, fast turnaround time, and an easy platform for prototyping distributed\nmass sensors with unprecedented mass resolution for this kind of devices....
This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for
multiple industrial protocols and compatible with different protocol versions. Targeting a wide
operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator
(VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization
scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several
bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feedforward
equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization.
The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied
an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of
0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane’s data
rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate
and can tune an equalization up to 10 dB....
This article describes an asynchronous split-CDAC-based SAR ADC with integrated input
PGA and an RV-Buffer. The split CDAC structure not only reduces the area of the ADC, but also
relieves the driving pressure of the input PGA and RV-Buffer. Using the input PGA instead of
the traditional input buffer as the driving circuit of the ADC increases the dynamic input range of
the ADC. The proposed on-chip RV-Buffer can provide 1.1 V positive and 0.1 V negative voltage,
avoiding the disturbance caused by off-chip reference. This prototype is implemented in a 65 nm
CMOS process and occupies an active area of 0.088 mm2. The input PGA can provide 0–18 dB
programmable gain with a step of 3 dB. Measurement results show that as the provided gain changes,
the ADC’s SNR is best, reaching 50.9 dB, and the SFDR is beat, reaching 62.35 dB at 50 MS/s....
This brief presents an analog front-end (AFE) for the detection of electroencephalogram
(EEG) signals. The AFE is composed of four sections, chopper-stabilized amplifiers, ripple suppression
circuit, RRAM-based lowpass FIR filter, and 8-bit SAR ADC. This is the first time that
an RRAM-based lowpass FIR filter has been introduced in an EEG AFE, where the bio-plausible
characteristics of RRAM are utilized to analyze signals in the analog domain with high efficiency.
The preamp uses the symmetrical OTA structure, reducing power consumption while meeting gain
requirements. The ripple suppression circuit greatly improves noise characteristics and offset voltage.
The RRAM-based low-pass filter achieves a 40 Hz cutoff frequency, which is suitable for the analysis
of EEG signals. The SAR ADC adopts a segmented capacitor structure, effectively reducing the
capacitor switching power consumption. The chip prototype is designed in 40 nm CMOS technology.
The overall power consumption is approximately 13 μW, achieving ultra-low-power operation....
This paper presents a differential 19.6–39.4 GHz broadband low-noise amplifier (LNA) in
65-nm CMOS technology. The LNA consists of two cascode stage and one common-source stage. To
achieve a wide bandwidth and low average noise figure, inter-stage peak-gain distribution technique
and transformer-based triple-coupled technique are developed. Besides, a new compact T-coil-based
network is proposed to neutralize the parasitic capacitors and enlarge the gain. The measure results
show that the 3-dB bandwidth is from 19.6 to 39.4 GHz, the maximum gain is 23.5 dB, and the noise
figure (NF) is from 3.7 to 5.8 dB. The dc power comsumption is 46 mW with 1V supply voltage. The
input P1dB is −17 dBm at 30 GHz....
This article presents a low power digital controlled oscillator (DCO) with an ultra low
power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled
topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty
cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further.
The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation
(SMIC) 40 nm CMOS process...........................
This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS)\ntransceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge\noutput driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated\ncommon mode voltage over process, voltage and temperature (PVT) variations. The receiver was\ncomposed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common\nmode voltage shifter with an error amplifier shifted the common mode voltage of the input\nsignal to the required range, thereby the following rail-to-rail comparator obtained the maximum\ntransconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology,\nand had an area of 1.46 mm2.The measured results showed that the output swing of the transmitter\nwas around 350 mV, with a root-mean-square (RMS) jitter of 3.65 firstname.lastname@example.org Gbps, and the power\nconsumption of each lane was 16.51 mW under a 1.8 V power supply....
A 24-GHz direct-conversion transmitter is proposed for in-cabin radar applications.\nThe proposed RF transmitter consists of an I/Q up-conversion mixer, an I/Q local (LO) oscillator\ngenerator, and a power amplifier. To improve the linearity of the I/Q up-conversion mixer, an inverter\ntransconductor with third-order intermodulation (IM3) distortion cancellation is proposed............................................
This paper presents a 10 bit 100 MS/s asynchronous successive approximation register
(SAR) analog-to-digital converter (ADC) without calibration for industrial control system (ICS)
applications. Several techniques are adopted in the proposed switching procedure to achieve better
linearity, power and area efficiency. A single-side-fixed technique is utilized to reduce the number
of capacitors; a parallel split capacitor array in combination with a partially thermometer coded
technique can minimize the switching energy, improve speed, and decrease differential non-linearity
(DNL). In addition, a compact timing-protection scheme is proposed to ensure the stability of the
asynchronous SAR ADC. The proposed ADC is fabricated in a 28 nm CMOS process with an active
area of 0.026 mm2. At 100 MS/s, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of
51.54 dB and a spurious free dynamic range (SFDR) of 55.12 dB with the Nyquist input. The measured
DNL and integral non-linearity (INL) without calibration are +0.37/0.44 and +0.48/0.63 LSB,
respectively. The power consumption is 1.1 mW with a supply voltage of 0.9 V, leading to a figure of
merit (FoM) of 35.6 fJ/conversion-step....
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