Current Issue : July-September Volume : 2025 Issue Number : 3 Articles : 5 Articles
In this work, an energy-efficient noise-shaping (NS) successive-approximation (SAR) capacitance-to-digital converter (CDC) is proposed. The interface is based on a direct-comparison technique, in which the sensor capacitance is compared directly to an on-chip binary weighted capacitive digital-to-analog converter (DAC). To implement NS, a 2nd order feed-forward loop filter processes the extracted residue at the end of each conversion cycle. Employing NS to achieve the target resolution leads to a small capacitive DAC and hence a small Si-area compared to the conventional SAR approach that would require a capacitive DAC with the same resolution as the overall CDC resolution. The proposed capacitive NS SAR sensor interface is designed and implemented in 130 nm CMOS technology for a 4 pF dynamic range and achieves an effective number of bits (ENOB) of 12.0 bits with a measurement time of 2.5 ms. The CDC dissipates 1.0 μA from a 0.8 V supply resulting in a figure of merit (FoM) of 488 fJ/conversion-step....
This paper presents a highly stable and integrated silicon-based carrier with broad application prospects. Traditional 800 G optical modules employ architectures based on aluminum nitride (AlN) carriers with externally mounted capacitors. However, such AlN-based architectures suffer from issues including high process complexity, elevated costs, poor environmental temperature adaptability, and difficulties in systematic crosstalk optimization. To address these challenges, this study conducted research on coplanar waveguide (CPW) transmission line structure design and optimization, high-density capacitor design and process implementation, and multi-channel crosstalk suppression. Based on these investigations, a silicon-based integrated carrier was designed and fabricated, incorporating resistors, capacitors, high-speed signal lines, and preformed AuSn structures. Test results demonstrate that the CPW transmission line structures fabricated on the silicon carrier exhibit excellent radio frequency performance with transmission losses below 1 dB within 67 GHz. The developed high-density capacitor structure achieves a remarkable capacitance density of 26.83 nF/mm2 and withstands voltages exceeding 24 V at 1 μA current, reaching state-of-the-art levels. This paper also proposes crosstalk reduction solutions including increased channel spacing, the addition of wave-absorbing materials, and the implementation of metal barriers. Experimental results confirm that the developed integrated carrier demonstrates outstanding performance and reliability in high-frequency communications and optoelectronic devices....
Schottky barrier thin-film transistors (SBTFTs) are promising for low-power electronics due to advantages such as low saturation voltage and high stability. In this study, we developed a high-performance bilayer IGZO SBTFT by combining a 4.7 nm atomic layer deposition (ALD) IGZO layer with an 11.8 nm sputtering IGZO layer, using platinum (Pt) and molybdenum (Mo) electrodes. The device exhibits dual-mode operation. In Schottky barrier TFT (SB-TFT) mode (Pt as source), the bilayer structure reduces defect density, achieving a very low saturation voltage (~0.4 V), high field-effect mobility (up to 20 cm²/V·s), and enhanced stability under stress conditions, including positive/negative bias and negative illumination. In quasi-Ohmic TFT (QO-TFT) mode (Pt as drain), the device retains conventional saturation behavior in output characteristics while delivering similar mobility and robust stability. This work provides a novel bilayer SBTFT design with dual functionality, enabling a higher current drive, improved stability, and flexibility for energy-efficient applications....
Today, many electronic circuits are required to be able to work effectively, even in environments exposed to ionizing radiation. This work examines the effects of ionizing radiation on shift registers realized in a bulk 16 nm FinFET technology, focusing on Single- Event Upset (SEU). An SEU occurs when a charged particle ionizes a sensitive node in the circuit, causing a stored bit to flip from one logical state to its opposite. This study estimates the saturation cross-section for the 16 nm FinFET technology and compares it with results from a 28 nm planar CMOS technology. The experiments were conducted at the SIRAD facility of INFN Legnaro Laboratories (Italy). The device under test was irradiated with the ion sources 58Ni and 28Si, both with different tilt angles, to assess the number of SEUs with different LET and range values. Additionally, the study evaluates the effectiveness of the radiation-hardened by design technique, specifically the Triple Modular Redundancy (TMR), which is a technique commonly employed in planar technologies. However, in this particular case study, TMR proved to be ineffective, and the reasons behind this limitation are analyzed along with potential improvements for future designs....
This paper presents a three-channel galvanic isolation interface in GaN technology. Driver, diagnostic, and control channels have been implemented in a two-die integrated system to perform an isolation interface for a high-performance power switching system. Chip-to-chip communication has been used, which is based on planar micro-antennas with on–off keying modulated RF carriers. This approach provides a high isolation rating by properly setting the distance between chips. Various innovation aspects are adopted with respect to previously published works. They mainly involve the receiver robustness thanks to the switched-capacitor bias control, a bidirectional data channel implementation for power section diagnostic, and a duty cycle distortion compensation for accurate PWM signal. Driver and control channels use RF carriers of about 2 GHz and 0.9 GHz and achieve 2 MHz and 0.5 MHz measured pulse width modulation signals, respectively. The bidirectional channel adopts an RF carrier of about 400 MHz and exhibits a maximum measured data rate as high as 10 Mb/s. Thanks to the extensive use of switched-capacitor circuit solutions, well-controlled behavior is achieved against the large process tolerances and temperature drifts of the GaN technology. The isolation interface is supplied at 6 V and occupies a die area of 7.6 mm2 for each chip....
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