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Inventi Impact: VLSI
publication date: 2013/10/15

DESIGN OF THE LOW POWER LEFT TO RIGHT TRUNCATED PARALLEL MULTIPLIERS
                  Wani V Patil

ABSTRACT
Multiplication is frequently required in Digital Signal Processing (DSP). Parallel multipliers provide a high-speed method for multiplication, but require large area for VLSI implementations. In most signal processing applications, a rounded product is desired to avoid growth in word-size. Truncated multiplication provides an efficient method for reducing the power dissipation and area of rounded parallel multipliers in digital signal processing systems. With this technique, the partial parallel multipliers are rounded to a shorter word size and the least-significant columns of the multiplication matrix are not used and the carry generated by these is added in most significant columns. In this paper a Left-to-right (LR) parallel multipliers are designed with the truncated scheme. In this paper, we will design both array structure and tree structure with compressors for LR and Right-to-Left parallel multipliers and compared their results. Simulation results show that LR multiplier with truncated scheme consumes 25% to 30% less power than Right-to-left (RL) multiplier with truncated scheme

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How to Cite This Article

Wani V Patil,  " DESIGN OF THE LOW POWER LEFT TO RIGHT TRUNCATED PARALLEL MULTIPLIERS ",  Inventi Impact: VLSI ,  Vol. 2013 , Article ID- " Inventi:evs/84/13 " 2013  [ cited 2014 Jul 30 ]  Available From  


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